PERFORMANCE FEATURES

12.5 ns Instruction Cycle Time @1.8 V (Internal), 80 MIPS

Sustained Performance

Single-Cycle Instruction Execution

Single-Cycle Context Switch

3-Bus Architecture Allows Dual Operand Fetches in

Every Instruction Cycle

Multifunction Instructions

Power-Down Mode Featuring Low CMOS Standby

Power Dissipation with 200 CLKIN Cycle Recovery

from Power-Down Condition

Low Power Dissipation in Idle Mode

INTEGRATION FEATURES

ADSP-2100 Family Code Compatible (Easy to Use

Algebraic Syntax), with Instruction Set Extensions

Up to 256K Bytes of On-Chip RAM, Configured as

Up to 48K Words Program Memory RAM

Up to 56K Words Data Memory RAM

Dual-Purpose Program Memory for Both Instruction and

Data Storage

Independent ALU, Multiplier/Accumulator, and Barrel

Shifter Computational Units

Two Independent Data Address Generators

Powerful Program Sequencer Provides Zero Overhead

Looping Conditional Instruction Execution

Programmable 16-Bit Interval Timer with Prescaler

100-Lead LQFP and 144-Ball Mini-BGA

SYSTEM INTERFACE FEATURES

Flexible I/O Allows 1.8 V, 2.5 V or 3.3 V Operation

All Inputs Tolerate up to 3.6 V Regardless of Mode

16-Bit Internal DMA Port for High-Speed Access to On-

Chip Memory (Mode Selectable)

4M-Byte Memory Interface for Storage of Data Tables

and Program Overlays (Mode Selectable)

8-Bit DMA to Byte Memory for Transparent Program and

Data Memory Transfers (Mode Selectable)

Programmable Memory Strobe and Separate I/O

Memory Space Permits “Glueless” System Design

Programmable Wait State Generation

Two Double-Buffered Serial Ports with Companding

Hardware and Automatic Data Buffering

Automatic Booting of On-Chip Program Memory from

Byte-Wide External Memory, e.g., EPROM, or through

Internal DMA Port

Six External Interrupts

13 Programmable Flag Pins Provide Flexible System

Signaling

UART Emulation through Software SPORT

Reconfiguration

ICE-Port? Emulator Interface Supports Debugging in

Final Systems