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MPC866TVR100A
| Processors | FREESCALE | PBGA-FW | $41.26 |
Maximum frequency operation of the external bus is 66 MHz
Single-issue, 32-bit core (compatible with Power Architecture technology) with 32, 32-bit general-purpose registers (GPRs)
The MPC866 Family provides enhanced ATM functionality as found on the MPC862. The MPC866 adds major new features available in "enhanced SAR" (ESAR) mode, including the following:
- Improved operation, administration and maintenance (OAM) support
- OAM performance monitoring (PM) support
- Multiple APC priority levels available to support a range of traffic pace requirements
- Port-to-port switching capability without the need for RAM-based microcode
- Simultaneous MII (100Base-T) and UTOPIA (half-duplex) capability
- Optional statistical cell counters per PHY
- UTOPIA level 2 compliant interface with added FIFO buffering to reduce the total cell transmission time. (The earlier UTOPIA level 1 specification is also supported.)
- Parameter RAM for both SPI and I2C can be relocated without RAM-based microcode
- Supports full-duplex UTOPIA both master (ATM side) and slave (PHY side) operation using a "split" bus
- AAL2/VBR functionality is ROM-resident
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
32 address lines
Memory controller (eight banks)
General-purpose timers
Fast Ethernet controller (FEC)
System integration unit (SIU)
Interrupts
Communications processor module (CPM)
Four baud rate generators
Four SCCs (serial communication controllers)
Two SMCs (serial management channels)
One SPI (serial peripheral interface)
One I2C (inter-integrated circuit) port
Time-slot assigner (TSA)
Parallel interface port (PIP)
PCMCIA interface
Debug interface
1.8 V Core and 3.3 V I/O operation with 5-V TTL compatibility
357-pin ball grid array (BGA) package
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